system verilog - In systemverilog, is it possible to conditionalize a parameterized type? -


in systemverilog, can conditionalize parameterized type?

i want like:

parameter is_r = 0, parameter type id_t = is_r ? r_t : d_t

my lint program not this, ideas? illegal?

no cannot this. systemverilog lrm allows 2 operations type parameters - assignment , equality. try using generate construct, code using conditional type has inside generated block.


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