Verilog carry lookahead adder -

`timescale 100ns/1ps  module carrylas_tb;  reg [7:0] a; reg [7:0] b; reg ci;  wire [7:0] sum; wire of; //overflow wire co;  integer i;  carrylas_8 cla(a,b,ci,sum,co,of);       initial begin   a=0; b=0; ci=0;  end   initial begin // possible cases   for(i=0; i<262144; i=i+1) // 2^18   #10 {a, b, ci} = i;   end  endmodule  module carrylas_8(a,b,ci,sum,co,of);  input [7:0] a,b;  input ci; // 0; add 1: subtract  output [7:0] sum; output co; output of;  wire[7:0] c;  wire[7:0] xb;  xor(xb[0],b[0],ci);  xor(xb[1],b[1],ci);  xor(xb[2],b[2],ci);  xor(xb[3],b[3],ci);  xor(xb[4],b[4],ci);  xor(xb[5],b[5],ci);  xor(xb[6],b[6],ci);  xor(xb[7],b[7],ci);  xor(of,c[7],c[6]);  xor(co,c[7],ci);  carryla_8 clas(a,xb,ci,sum,co);   endmodule   module carryla_8(a,b,ci,sum,co);  input [7:0] a,b; input ci;  output [7:0] sum; output co;  wire [7:0] sum; wire cm,co;  carryla_4 cla0(a[3:0],b[3:0],ci,sum[3:0],cm); carryla_4 cla1(a[7:4],b[7:4],cm,sum[7:4],cm);  endmodule   module carryla_4(a,b,ci,sum,co);  input [3:0] a,b;  input ci; // 0; add 1: subtract  output [3:0] sum;  output co;  wire[3:0] g,p,cout; wire g0,p0; wire[9:0] w;  , a0(g[0],a[0],b[0]);  , a1(g[1],a[1],b[1]);  , a2(g[2],a[2],b[2]);  , a3(g[3],a[3],b[3]);    xor x0(p[0],a[0],b[0]); xor x1(p[1],a[1],b[1]); xor x2(p[2],a[2],b[2]); xor x3(p[3],a[3],b[3]);  , and0(w[0],p[0],ci); or or0(cout[0],g[0],w[0]);  , and1(w[1],p[1],p[0],ci); , and2(w[2],p[1],g[0]); or or1(cout[1],g[1],w[2],w[1]);  , and3(w[3],p[2],p[1],p[0],ci); , and4(w[4],p[2],p[1],g[0]); , and5(w[5],p[2],g[1]); or or2(cout[2],g[2],w[5],w[4],w[3]);  , and6(w[6],p[3],p[2],p[1],g[0]); , and7(w[7],p[3],p[2],g[1]); , and8(g[2],a[2],b[2]);  or or3(g0,g[3],w[8],w[7],w[6]);  , and9(p0,p[3],p[2],p[1],p[0]);  , and10(w[9],p0,ci); or or4(cout[3],g0,w[9]);  , and11(co,cout[3],1);  xor xor0(sum[0],p[0],ci); xor xor1(sum[1],p[1],cout[0]); xor xor2(sum[2],p[2],cout[1]); xor xor3(sum[3],p[3],cout[2]);    endmodule 

this verilog code. simulated well, result kinda sucks. 'sum' produces values xs, , 'co', 'of'(overflow detection) xs. couldn't find out problem is. might carry think. me this? appreciated. in advance.

captured waveform attached

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you have multiple drivers on wire [8:0] c. in generate have:

or o1 (c[i+1],g[i],q[i]); 

and have fulladder instances drive c:

fulladder a0(a[0],b[0],ci,sum[0],c[0]); 

i can't reason won't simulate, make not function correctly.